`include "common_def.v"
`include "decode_def.v"
module MODULE_B_Judge (
	input							clk_i,
	input							rst_i,
	input							add_nouse_inst_i,
	input							add_start_i,
	input	[31:0]			inst_i,
	input	[`WIDTH-1:0]	src1_i,
	input	[`WIDTH-1:0]	src2_i,
	output							pc_jump_o,
	output 	[`PC_NUM-1:0] pc_key_o
);
wire  ignore_jump_o;

wire is_B_type;
wire is_J_type;
wire is_mret;
wire is_ecall;
wire is_jal_J;
wire is_jalr_I;
wire pc_key_beq;
wire pc_key_bne;
wire pc_key_bge;
wire pc_key_blt;
wire pc_key_bltu;
wire pc_key_bgeu;
wire [`WIDTH-1:0]sub_result;
assign is_B_type = (inst_i[6:0] == `B_OPCODE);
assign is_J_type = is_jal_J|0;
assign is_jal_J = (inst_i[6:0] == `JAL_OPCODE);
assign is_jalr_I = (inst_i[6:0] == `JALR_OPCODE)&(inst_i[14:12] == `JALR_FUNCT3);
assign is_ecall = inst_i[31:0] == `ECALL;
assign is_mret = inst_i[31:0] == `MRET;


assign sub_result[`WIDTH-1:0] = src1_i[`WIDTH-1:0] - src2_i[`WIDTH-1:0];
assign pc_key_beq = is_B_type & (inst_i[14:12] == `BEQ_FUNCT3) &( sub_result[`WIDTH-1:0] == 0);
assign pc_key_bne = is_B_type & (inst_i[14:12] == `BNE_FUNCT3) &( sub_result[`WIDTH-1:0]!=0);
assign pc_key_bge = is_B_type & (inst_i[14:12] == `BGE_FUNCT3) &(sub_result[`WIDTH-1] ==1'b0);
assign pc_key_blt = is_B_type & (inst_i[14:12] == `BLT_FUNCT3) &(sub_result[`WIDTH-1] ==1'b1);
assign pc_key_bltu = is_B_type & (inst_i[14:12] == `BLTU_FUNCT3) &(src1_i[`WIDTH-1:0] < src2_i[`WIDTH-1:0] );
assign pc_key_bgeu= is_B_type & (inst_i[14:12] == `BGEU_FUNCT3) &(src1_i[`WIDTH-1:0]>=src2_i[`WIDTH-1:0]);

wire pc_key_0_o;
wire pc_key_0;
assign pc_key_0=(pc_key_beq|pc_key_bne|pc_key_bge|pc_key_blt|pc_key_bltu|pc_key_bgeu);
assign pc_key_0_o = (pc_key_0)&(~ignore_jump_o);

wire pc_jump_1;
//ignore_jump
wire add_nouse_inst_r;
Reg #(1,0) add_nouse_inst_reg(clk_i,rst_i,add_start_i?0:add_nouse_inst_i,add_nouse_inst_r,add_start_i|add_nouse_inst_i);
assign pc_jump_1 = pc_key_0_o;
assign ignore_jump_o = (add_nouse_inst_i|add_nouse_inst_r);//&(~add_start_i); 
	//gen pc_key,001 use alu result,010 use alu result but set the last bit zero,100 use csr_data, default use pc + 4 
	//B inst not decode at here but in B_judge the decode result will be add to
	//pc_key_o[0] and pc_jump_o
	//pc_jump_o should consider is_mret and is_ecall_o it is not done yet
assign pc_key_o[0] = is_J_type|pc_key_0_o;//|pc_key_beq|pc_key_bne|pc_key_bge|pc_key_blt|pc_key_bltu|pc_key_bgeu|0;
assign pc_key_o[1] = is_jalr_I| 0;//not finished yet jalr
assign pc_key_o[2] = is_mret|is_ecall;
assign pc_jump_o = ((is_J_type | is_jalr_I|is_mret|is_ecall)&(~ignore_jump_o))|pc_jump_1;
endmodule
